//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*

THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  
    usbOtg.h

Abstract:  
    This module defines the constants for USB peripheral
    controller.    

Functions:

    
--*/


#ifndef _USBOTG_H

#define    _USBOTG_H

#define USB_CHARGER

#define USB_DMA_ENABLE 1
#define USB_RNDIS_WARNING 2
#define USB_RNDIS_INFO         3
#define USB_RNDIS_ERROR       1
#define USB_RNDIS_BULK_RECV 7
#define USB_RNDIS_ISR          8
#define USB_RNDIS_BULK_SEND 9

#define EP0LEN          64
#define EP1LEN          64
#define EP2LEN          64
#define EP3LEN          sizeof(INTERRUPT_DATA)        
#ifdef K3_B831_CODE
#define ECS_OTG_BASE_ADDRESS 0x30002000
#else
#define ECS_OTG_BASE_ADDRESS 0x92002000
/*DMA BUFFER BASE ADDRESS*/
//#define USB_DMA_BUFFER_ADDR 0xad800000
#define USB_DMA_BUFFER_ADDR ((PBYTE)(USB_BUF_BASE)+ 0x2000)
#define USB_DMA_RECV_OFFSET 0x2000
#endif

#define ECS_SPLIT_MAX_SIZE  16*64
#define ECS_SPLIT_M_PLOAD   16

#ifdef K3_B831_CODE
/*Bit Mask definitions*/
#define BIT_0 0x00000001
#define BIT_1 0x00000002
#define BIT_2 0x00000004
#define BIT_3 0x00000008
#define BIT_4 0x00000010
#define BIT_5 0x00000020
#define BIT_6 0x00000040
#define BIT_7 0x00000080
#define BIT_8 0x00000100
#define BIT_9 0x00000200
#define BIT_10 0x00000400
#define BIT_11 0x00000800
#define BIT_12 0x00001000
#define BIT_13 0x00002000
#define BIT_14 0x00004000
#define BIT_15 0x00008000
#define BIT_16 0x00010000
#define BIT_17 0x00020000
#define BIT_18 0x00040000
#define BIT_19 0x00080000
#define BIT_20 0x00100000
#define BIT_21 0x00200000
#define BIT_22 0x00400000
#define BIT_23 0x00800000
#define BIT_24 0x01000000
#define BIT_25 0x02000000
#define BIT_26 0x04000000
#define BIT_27 0x08000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000

/*system control regs were used by USB*/
#define SC_BASEADDR  			0x20040000
#define SC_PERCTRL0                      0x01c   /*32 bit */
#define SC_PERCTRL1                      0x020   /*32 bit */
#define SC_PEREN                     	0x024   /* 32 bit */
#define SC_RSTCTRL2                      0x048   /*32 bit */
#define SC_PERCTRL5                      0x058   /*32 bit */

#define SC_REG_SET(Addr, Value ) \
            (*((volatile UINT32 *)(Addr)) = (Value))
#define SC_REG_GET(Addr, ValueAddr)\
            (*(ValueAddr) = *((volatile UINT32 *)(Addr)))
#define SC_REG_BIT_SET(Addr, bitMask)\
            (*((volatile UINT32 *)(Addr)) =(*((volatile UINT32 *)(Addr))|bitMask))
#define SC_REG_BIT_CLEAR(Addr, bitMask)\
            (*((volatile UINT32 *)(Addr)) = ((*((volatile UINT32 *)(Addr)))& ~(bitMask)))
#endif

    /* Common USB registers */
#define ECS_OTG_FADDR                     0x00   /* 8 bit */
#define ECS_OTG_POWER                     0x01   /* 8 bit */
#define ECS_OTG_INTRTX                    0x02  
#define ECS_OTG_INTRRX                    0x04
#define ECS_OTG_INTRTXE                  0x06  
#define ECS_OTG_INTRRXE                  0x08  
#define ECS_OTG_INTRUSB                  0x0A   /* 8 bit */
#define ECS_OTG_INTRUSBE                0x0B   /* 8 bit */
#define ECS_OTG_FRAME                      0x0C  
#define ECS_OTG_INDEX                      0x0E   /* 8 bit */
#define ECS_OTG_TESTMODE               0x0F   /* 8 bit */
#define ECS_OTG_TARGET_FUNCTION_BASE      0x80   /* 8 bit */
    /* Indexed registers */
#define ECS_OTG_TXMAXP                    0x10
#define ECS_OTG_CSR0                         0x12
#define ECS_OTG_TXCSR                      0x12
#define ECS_OTG_RXMAXP                   0x14
#define ECS_OTG_RXCSR                      0x16
#define ECS_OTG_COUNT0                   0x18
#define ECS_OTG_RXCOUNT                 0x18
#define ECS_OTG_TXTYPE                    0x1A    /* 8 bit, only valid in Host mode */
#define ECS_OTG_TYPE0                      0x1A    /* 2 bit, only valid in MDRC Host mode */
#define ECS_OTG_NAKLIMIT0              0x1B    /* 8 bit, only valid in Host mode */
#define ECS_OTG_TXINTERVAL             0x1B    /* 8 bit, only valid in Host mode */
#define ECS_OTG_RXTYPE                     0x1C    /* 8 bit, only valid in Host mode */
#define ECS_OTG_RXINTERVAL             0x1D    /* 8 bit, only valid in Host mode */
#define ECS_OTG_CONFIGDATA            0x1F    /* 8 bit */
#define ECS_OTG_FIFOSIZE                  0x1F    /* 8 bit */    
    /* FIFOs for Endpoints 0 - 15, 32 bit word boundaries */
#define ECS_OTG_FIFO_EP0                  0x20
#define ECS_OTG_FIFO_EP1                  0x24
#define ECS_OTG_FIFO_EP2                  0x28
#define ECS_OTG_FIFO_EP3                  0x2C
    /* Additional Control Registers */
#define    ECS_OTG_DEVCTL                    0x60       /* 8 bit */    
    /* Dynamic FIFO sizing */
#define ECS_OTG_TXFIFOSZ                   0x62   /* 8 bit, TxFIFO size */
#define ECS_OTG_RXFIFOSZ                   0x63    /* 8 bit, RxFIFO size */
#define ECS_OTG_TXFIFOADD                0x64    /* 16 bit, TxFIFO address */
#define ECS_OTG_RXFIFOADD                0x66    /* 16 bit, RxFIFO address */

    /*
     *for DMA operation register
     */
#define ECS_OTG_DMA_BASE                  ( 0x200)
    /*value of channel range from 0 to CHANNEL_MAX_NUM-1*/
#define ECS_OTG_DMA_INTR                   ( 0x200)
#define ECS_OTG_DMA_CTL(channel)          (ECS_OTG_DMA_BASE + 0x10*(channel) + 4)
#define ECS_OTG_DMA_ADDR(channel)         (ECS_OTG_DMA_BASE + 0x10*(channel) + 8)
#define ECS_OTG_DMA_COUNT(channel)        (ECS_OTG_DMA_BASE + 0x10*(channel) + 0xc)


    /**************************************************************************
     Macros for flag  operations
     ***************************************************************************/
#define ECS_SET_FLAG(_M, _F)                   ((_M) |= (_F))
#define ECS_CLEAR_FLAG(_M, _F)                 ((_M) &= ~(_F))
#define ECS_CLEAR_FLAGS(_M)                    ((_M) = 0)
#define ECS_TEST_FLAG(_M, _F)                  (((_M) & (_F)) != 0)
#define ECS_TEST_FLAGS(_M, _F)                 (((_M) & (_F)) == (_F))

    /*MUSBHDRC Register bit masks*/

    /* POWER */
#define ECS_OTG_POWER_ISOUPDATE            0x80 
#define    ECS_OTG_POWER_SOFTCONN          0x40
#define    ECS_OTG_POWER_HSENAB            0x20
#define    ECS_OTG_POWER_HSMODE            0x10
#define ECS_OTG_POWER_RESET                0x08
#define ECS_OTG_POWER_RESUME               0x04
#define ECS_OTG_POWER_SUSPENDM             0x02
#define ECS_OTG_POWER_ENSUSPEND            0x01
    /* INTRTX, INTRTXE*/
#define ECS_OTG_INTRTX_DISABLE             0x0000
#define ECS_OTG_INTRTX_EP3_BULK            0x0008
#define ECS_OTG_INTRTX_EP2_BULK            0x0004
#define ECS_OTG_INTRTX_EP1_BULK            0x0002
#define ECS_OTG_INTRTX_EP0_CTRL            0x0001
    /* INTRRX, INTRRXE*/
#define ECS_OTG_INTRRX_DISABLE             0x0000
#define ECS_OTG_INTRRX_EP3_BULK            0x0008
#define ECS_OTG_INTRRX_EP2_BULK            0x0004
#define ECS_OTG_INTRRX_EP1_BULK            0x0002
    /* INTRUSB, INTRUSBE */
#define ECS_OTG_INTRUSB_DISABLE            0x00
#define ECS_OTG_INTR_VBUSERROR             0x80   /* only valid when A device */
#define ECS_OTG_INTR_SESSREQ               0x40   /* only valid when A device */
#define ECS_OTG_INTR_DISCONNECT            0x20
#define ECS_OTG_INTR_CONNECT               0x10   /* only valid in Host mode */
#define ECS_OTG_INTR_SOF                   0x08 
#define ECS_OTG_INTR_RESET                 0x04
#define ECS_OTG_INTR_RESUME                0x02
#define ECS_OTG_INTR_SUSPEND               0x01   /* only valid in Peripheral mode */
    /* TESTMODE */
#define ECS_OTG_TEST_FIFO_ACCESS              0x40
#define ECS_OTG_TEST_FORCEFS               0x20
#define ECS_OTG_TEST_FORCEHS               0x10
#define ECS_OTG_TEST_PACKET                0x08
#define ECS_OTG_TEST_K                     0x04
#define ECS_OTG_TEST_J                     0x02
#define ECS_OTG_TEST_SE0_NAK               0x01
    /* DEVCTL */
#define ECS_OTG_DEVCTL_BDEVICE             0x80   
#define ECS_OTG_DEVCTL_FSDEV               0x40
#define ECS_OTG_DEVCTL_LSDEV               0x20
#define ECS_OTG_DEVCTL_HM                  0x04
#define ECS_OTG_DEVCTL_HR                  0x02
#define ECS_OTG_DEVCTL_SESSION             0x01
    /* CSR0 in Peripheral mode */
#define    ECS_OTG_CSR0_FLUSHFIFO          0x0100
#define ECS_OTG_CSR0_SVDSETUPEND           0x0080
#define ECS_OTG_CSR0_SVDRXPKTRDY           0x0040
#define ECS_OTG_CSR0_SENDSTALL             0x0020
#define ECS_OTG_CSR0_SETUPEND              0x0010
#define ECS_OTG_CSR0_DATAEND               0x0008
#define ECS_OTG_CSR0_SENTSTALL             0x0004
#define ECS_OTG_CSR0_TXPKTRDY              0x0002
#define ECS_OTG_CSR0_RXPKTRDY              0x0001
    /* CONFIGDATA */
#define ECS_OTG_CONFIGDATA_DMA             0x40
#define ECS_OTG_CONFIGDATA_BIGENDIAN       0x20
#define ECS_OTG_CONFIGDATA_HBRXE           0x10
#define ECS_OTG_CONFIGDATA_HBTXE           0x08
#define ECS_OTG_CONFIGDATA_DYNFIFO         0x04
#define ECS_OTG_CONFIGDATA_SOFTCONE        0x02
#define ECS_OTG_CONFIGDATA_UTMIDW          0x01   /* data width 0 => 8bits, 1 => 16bits */
    /* TXCSR in Peripheral mode */
#define ECS_OTG_TXCSR_AUTOSET              0x8000
#define ECS_OTG_TXCSR_ISO                  0x4000
#define ECS_OTG_TXCSR_MODE                 0x2000
#define ECS_OTG_TXCSR_DMAENAB              0x1000
#define ECS_OTG_TXCSR_FRCDATATOG           0x0800
#define ECS_OTG_TXCSR_DMAMODE              0x0400
#define ECS_OTG_TXCSR_DMAMODE0             0x0000
#define ECS_OTG_TXCSR_INCOMPTX             0x0080
#define ECS_OTG_TXCSR_CLRDATATOG           0x0040
#define ECS_OTG_TXCSR_SENTSTALL            0x0020
#define ECS_OTG_TXCSR_SENDSTALL            0x0010
#define ECS_OTG_TXCSR_FLUSHFIFO            0x0008
#define ECS_OTG_TXCSR_UNDERRUN             0x0004
#define ECS_OTG_TXCSR_FIFONOTEMPTY         0x0002
#define ECS_OTG_TXCSR_TXPKTRDY             0x0001
    /* RXCSR in Peripheral mode */
#define ECS_OTG_RXCSR_AUTOCLEAR            0x8000
#define ECS_OTG_RXCSR_ISO                  0x4000
#define ECS_OTG_RXCSR_DMAENAB              0x2000
#define ECS_OTG_RXCSR_DISNYET              0x1000
#define ECS_OTG_RXCSR_DMAMODE              0x0800
#define ECS_OTG_RXCSR_INCOMPRX             0x0100
#define ECS_OTG_RXCSR_CLRDATATOG           0x0080
#define ECS_OTG_RXCSR_SENTSTALL            0x0040
#define ECS_OTG_RXCSR_SENDSTALL            0x0020
#define ECS_OTG_RXCSR_FLUSHFIFO            0x0010
#define ECS_OTG_RXCSR_DATAERROR            0x0008
#define ECS_OTG_RXCSR_OVERRUN              0x0004
#define ECS_OTG_RXCSR_FIFOFULL             0x0002
#define ECS_OTG_RXCSR_RXPKTRDY             0x0001


    /*ECS_OTG_DMA_INTR when use DMA*/
#define ECS_OTG_DMA_INTR_1                 0x0001
#define ECS_OTG_DMA_INTR_2                 0x0002
#define ECS_OTG_DMA_INTR_3                 0x0004
#define ECS_OTG_DMA_INTR_4                 0x0008


    /* USBIP endpoints */

#define USBIP_NUM_ENDPOINTS     8/* number of endpoints, CTRL-OUT, CTRL-IN, INT-IN, BULK-IN, BULK-OUT */
    /* NOTE: By convention, the target always places the endpoints which
     * are best suited for the default control channel at the beginning
     * of the endpoint array, with the USB_DIR_OUT (host->device) endpoint
     * first, followed by the USB_DIR_IN endpoint.
     */
#define USBIP_ENDPOINT_0_INDEX 0
#define USBIP_ENDPOINT_1_INDEX 1
#define USBIP_ENDPOINT_2_INDEX 2
#define USBIP_ENDPOINT_3_INDEX 3

    /* max endpoint packet lengths */
#define USBIP_MAX_PKT_CONTROL           0x40
#define USBIP_MAX_PKT_ENDPOINT_1_IN        0x40
#define USBIP_MAX_PKT_ENDPOINT_1_OUT        0x40
#define USBIP_MAX_PKT_ENDPOINT_2_IN        0x8
#define USBIP_MAX_PKT_ENDPOINT_2_OUT        0x40
#define USBIP_MAX_PKT_ENDPOINT_3_IN        0x40
#define USBIP_MAX_PKT_ENDPOINT_3_OUT        0x40

    /* DMA Mask */
#define ECS_OTG_DMA_CNTL_ENABLE            0x0001
#define ECS_OTG_DMA_CNTL_RX                0x0000
#define ECS_OTG_DMA_CNTL_TX                0x0002
#define ECS_OTG_DMA_CNTL_MODE0             0x0000
#define ECS_OTG_DMA_CNTL_MODE1             0x0004
#define ECS_OTG_DMA_CNTL_INTE              0x0008
#define ECS_OTG_DMA_CNTL_ENDNUM            0x00f0
#define ECS_OTG_DMA_CNTL_BUSERR            0x0100
#define ECS_OTG_DMA_CNTL_BURSTMODE         0x0600

#define USB_DMA_DATA_LENGTH 1600

    /*
     * for system control
     */
    /* Defined by the OTG Slave */
#define EPFIFOSIZE      (0x40)/*64bytes for every endpoints*/
/*SCPERCTRL2*/
#define SCPERCTRL2_RST    0x80000000
/*ULPI_VBUS_CONTROL*/
#define ULPI_VBUS_CONTROL_USEEXTBUSIND 0x02
#define ULPI_VBUS_CONTROL_USEEXTVBUS 0x01

/*ULPI_CAR_KIT_CONTROL*/
#define ULPI_CAR_KIT_CONTROL_DISABLEUTMI 0x01
#define ULPI_CAR_KIT_CONTROL_CARKITACTIVE 0x02
#define ULPI_CAR_KIT_CONTROL_ALTINTEVENT 0x04
#define ULPI_CAR_KIT_CONTROL_CANCELCARKIT 0x08/*(self cleared)*/
#define ULPI_CAR_KIT_CONTROL_RXCMDEVENT 0x10
#define ULPI_CAR_KIT_CONTROL_CARKITACTIVEEND 0x20

/*ULPI_INT_MASK*/
#define ULPI_INT_MASK_REGINTEN 0x01
#define ULPI_INT_MASK_ALTINTEN 0x02
#define ULPI_INT_MASK_ACTIVEENDINTEN 0x04
#define ULPI_INT_MASK_RXCMDINTEN  0x08

/*ULPI_INT_SRC*/
#define ULPI_INT_SRC_REGINT 01
#define ULPI_INT_SRC_ALTINT 02
#define ULPI_INT_SRC_ACTIVEENDINT 04
#define ULPI_INT_SRC_RXCMDINT 08

/*ULPI_REG_CONTROL*/
#define ULPI_REG_CONTROL_ULPIREGREQ 01
#define ULPI_REG_CONTROL_ULPIREGCMPLT 02
#define ULPI_REG_CONTROL_ULPIRDNWR 04

/*isp1504 registers*/
#define ISP_FUNCTION_CTRL_REG 0x04    /*(04-06)*/
#define ISP_INTERFACE_CTRL_REG 0x07   /*07-09*/
#define ISP_OTG_CTRL_REG 0x0A               /*(0A-0C)*/
#define ISP_INTERFACE_EDG_INT 0x0D      /*0D-0F*/


#define ECS_USB_VIRTUAL_ADDRESS  (gRndisUsb.pucBaseAddress)
#define ECS_USB_REG_SET(Addr, Value ) \
               (*((volatile UINT32 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (Value))

#define ECS_USB_REG_GET(Addr, ValueAddr)\
                (*(ValueAddr) = *((volatile UINT32 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)))

#define ECS_USB_REG_BIT_SET(Addr, bitMask)\
                (*((volatile UINT32 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) =(*((volatile UINT32 *)(ECS_USB_VIRTUAL_ADDRESS+Addr))|bitMask))//(OUTPORT32((UINT32 *)Addr,(*((volatile UINT32 *)(Addr))|bitMask)))//(*((volatile UINT32 *)(Addr)) = (*((volatile UINT32 *)(Addr))) | (bitMask))
//// 
#define ECS_USB_REG_BIT_CLEAR(Addr, bitMask)\
                  (*((volatile UINT32 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = ((*((volatile UINT32 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)))& ~(bitMask)))//(OUTPORT32((UINT32 *)Addr,((*((volatile UINT32 *)(Addr)))& ~(bitMask))))//(*((volatile UINT32 *)(Addr)) = (*((volatile UINT32 *)(Addr))) & ~(bitMask))// // 
#define ECS_USB_REG16_SET(Addr, Value)\
                (*((volatile UINT16 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (Value))

#define ECS_USB_REG16_GET(Addr, ValueAddr)\
                (*(ValueAddr) = *((volatile UINT16 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)))

#define ECS_USB_REG16_BIT_SET(Addr, bitMask)\
    (*((volatile UINT16 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (*((volatile UINT16 *)(ECS_USB_VIRTUAL_ADDRESS+Addr))) | (bitMask))

#define ECS_USB_REG16_BIT_CLEAR(Addr, bitMask)\
        (*((volatile UINT16 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (*((volatile UINT16 *)(ECS_USB_VIRTUAL_ADDRESS+Addr))) & ~(bitMask))

#define ECS_USB_REG8_SET(Addr, Value ) \
                (*((volatile UINT8 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (Value))

#define ECS_USB_REG8_GET(Addr, ValueAddr)\
                (*(ValueAddr) = *((volatile UINT8 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)))

#define ECS_USB_REG8_BIT_SET(Addr, bitMask)\
    (*((volatile UINT8 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (*((volatile UINT8 *)(ECS_USB_VIRTUAL_ADDRESS+Addr))) | (bitMask))

#define ECS_USB_REG8_BIT_CLEAR(Addr, bitMask)\
        (*((volatile UINT8 *)(ECS_USB_VIRTUAL_ADDRESS+Addr)) = (*((volatile UINT8 *)(ECS_USB_VIRTUAL_ADDRESS+Addr))) & ~(bitMask))
     
#define SET_CONTROL_LINE_STATE  0x22   
#define    BMREQUESTTYPE_CLASS        0x20
#define    BMREQUESTTYPE_VENDOR    0x40



#define    CS_INTERFACE    0x24
#define    CS_ENDPOINT        0x25

//
//    These are required in order to link to the MDD code..
//    Debug Zones 8..13 are for PDD usage..
//

#define    ZONE_INT        1//DEBUGZONE(8)
#define    ZONE_EP0        1//DEBUGZONE(9)
#define    ZONE_EP         1//DEBUGZONE(10)
#define ZONE_FIFO       1//DEBUGZONE(11)
#define    ZONE_PDD    1//    DEBUGZONE(12)

//
//    Global defines controlling PDD behaviour and affecting memory usage.
//    

#define    MAX_INCOMING_BUFFER                8192    //    MAX RNDIS_PACKET size.

typedef struct _INTERRUPT_DATA
{
    DWORD        Notification;
    DWORD        dwReserved;
    
}    INTERRUPT_DATA, *PINTERRUPT_DATA;


//
//  Sub debugging flag..
//

#define FULL_EP0_DEBUG      0x01
#define FULL_EP1_DEBUG      0x01
  
//
//    Standard Chapter 9 definition
//

typedef struct
{
    UCHAR    bmRequest; 
    UCHAR    bRequest;
    USHORT    wValue;
    USHORT    wIndex;
    USHORT    wLength;
} SETUP_PACKET, *PSETUP_PACKET;


//
//    Request Codes
//

#define GET_STATUS                0x00    
#define CLEAR_FEATURE            0x01
#define SET_FEATURE                0x03
#define SET_ADDRESS                0x05
#define GET_DESCRIPTOR            0x06
#define SET_DESCRIPTOR            0x07
#define GET_CONFIG                0x08
#define SET_CONFIG                0x09
#define GET_INTERFACE            0x0a
#define SET_INTERFACE            0x0b
#define SET_CONTROL_LINE_STATE  0x22   // Device specific request

//
//    Descriptor Types
//

#define DEVICE                    0x01
#define CONFIGURATION            0x02
#define STRING                    0x03
#define INTERFACE                0x04
#define ENDPOINT                0x05

#define MAX_CTRL_DATA_LENGTH  0x64

////////////////////////////////////////////////////////////////////////////////
//    Global var used by this module..
//

#define    EP0_MAX_RECEIVE_BUFFER  1024

typedef    struct
{
    DWORD                pucBaseAddress;
    DWORD                pucGPIOAddress;
    DWORD                pucSysAddress;
    ULONG                ulIRQ;
    DWORD                dwSysIntr;    
    BOOL                bConnected;
    BYTE                bUsbAddress;

    //
    //    EP0 related operations..
    //
    
    BOOL                bSending;    
    LIST_ENTRY            listTxRndisMessageQueue;
    PDATA_WRAPPER       pCurrentSendRndisMessage;
    PBYTE                pbCurrentSend;
    DWORD                dwCurrentSendSizeLeft;
    UCHAR               ucScratchBuffer;
    

    //
    //  Make it array of DWORD to get DWORD alignment.
    //    
    DWORD                pbEP0ReceiveBuffer[EP0_MAX_RECEIVE_BUFFER/sizeof(DWORD)];

    DATA_WRAPPER        EP0DataWrapper;            
    DWORD               dwExpectedRxSize;
    DWORD               dwTotalReceived;
    PBYTE               pbCurrentRx;

    //
    //  EP1 related operations..
    //

    PDATA_WRAPPER       pEP1DataWrapper;

    //
    //  EP2 related operations..
    //

    PDATA_WRAPPER       pEP2DataWrapper;
    PBYTE               pbEP2CurrentSend;
    DWORD               dwEP2TotalSent;
    UCHAR              ep0Data[MAX_CTRL_DATA_LENGTH];    
    BOOL                bEP2ShortPacketSent;
    BOOL                bEP0ShortPacketSent;
    BOOL                bIgReset;
    UCHAR               MacAddress[6];
    PUCHAR    pucEP0Data;
    UINT32       IERState;
    DWORD      ep0ReadBuffer[16];
    UCHAR      ep1RecvDmaChl;
    UCHAR      ep1SendDmaChl;

}    RNDIS_USB;    


#endif    // _NETUSB_H
